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this document is a general product descripti on and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no pat ent licenses are implied. rev. 0.5 / feb. 2006 1 HY5DU561622CTP 256m(16mx16) gddr sdram HY5DU561622CTP
rev. 0.5 / feb. 2006 2 1 HY5DU561622CTP revision history revision no. history draft date remark 0.1 defined target spec. aug. 2003 0.2 supports pb free parts for each speed grade sep. 2003 0.3 insert ac overshoot comment aug. 2004 0.4 tras_max change sep. 2004 0.5 tras_min & tqhs change oct. 2004
rev. 0.5 / feb. 2006 3 1 HY5DU561622CTP preliminary description the hynix HY5DU561622CTP is a 268,435,456-bit cmos double data rate(ddr) synchronous dram, ideally suited for the point-to-point applications which requires high bandwidth. the hynix 16mx16 ddr sdrams offer fully synchronous operations referenced to both rising and falling edges of the clock. while all addresses and control inputs are latched on th e rising edges of the ck (fal ling edges of the /ck), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. the data paths are inter- nally pipelined and 2-bit prefetched to achieve very high bandwidth. all input and output voltage levels are compatible with sstl_2. features ? 2.5v +/-5% vdd and vddq power supply supports 250 / 200 / 166mhz ? 2.6v vdd/vddq wide range min/max power supply supports 300/275mhz ? 2.8v +/-0.1v vdd and vddq power supply supports 350mhz ? all inputs and outputs are compatible with sstl_2 interface ? jedec standard 400mil 66pin tsop-ii with 0.65mm pin pitch ? fully differential clock inputs (ck, /ck) operation ? double data rate interface ? source synchronous - data transaction aligned to bidirectional data strobe (dqs) ? x16 device has 2 bytewide data strobes (ldqs, udqs) per each x8 i/o ? data outputs on dqs edges when read (edged dq) data inputs on dqs centers when write (centered dq) ? data(dq) and write masks(dm) latched on the both rising and falling edges of the data strobe ? all addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock ? write mask byte controls by ldm and udm ? programmable /cas latency 3 / 4 supported ? programmable burst length 2 / 4 / 8 with both sequential and interleave mode ? internal 4 bank operations with single pulsed /ras ? tras lock-out function supported ? auto refresh and self refresh supported ? 4096 refresh cycles / 32ms ? full, half and matched impedance(weak) strength driver option controlled by emrs ordering information note) hynix supports pb free parts for each speed grade with same specification, except pb free material. we'll add "p" character after "t" for pb free product. for example, the part number of 300mhz pb free product is HY5DU561622CTP-33. part no. power supply clock frequency max data rate interface package HY5DU561622CTP-28 vdd=2.8v vddq=2.8v 350mhz 700mbps/pin sstl-2 400mil 66pin tsop-ii HY5DU561622CTP-33 vdd=2.6v vddq=2.6v 300mhz 600mbps/pin HY5DU561622CTP-36 275mhz 550mbps/pin HY5DU561622CTP-4 vdd=2.5v vddq=2.5v 250mhz 500mbps/pin HY5DU561622CTP-5 200mhz 400mbps/pin HY5DU561622CTP-6 166mhz 333mbps/pin
rev. 0.5 / feb. 2006 4 1 HY5DU561622CTP pin configuration row and column address table items 16mx16 organization 4m x 16 x 4banks row address a0 ~ a12 column address a0 ~ a8 bank address ba0, ba1 auto precharge flag a10 refresh 4k 400 mil x 875mil 66 pin tsop - ii 0.65mm pin pitch top view v dd dq0 vddq dq1 dq2 v ssq dq3 dq4 v ddq dq5 dq6 v ssq dq7 nc v ddq ldqs nc v dd nc ldm /we /cas /ras /cs nc ba0 ba1 a 10/ap a0 a1 a2 a3 v dd v ss dq15 v ssq dq14 dq13 v ddq dq12 dq11 v ssq dq10 dq9 v ddq dq8 nc v ssq udqs nc v ref v ss udm /clk clk cke nc a12 a11 a9 a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
rev. 0.5 / feb. 2006 5 1 HY5DU561622CTP pin description pin type description ck, /ck input clock: ck and /ck are differen tial clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of /ck. output (read) data is referenced to the crossings of ck and /ck (both directions of crossing). cke input clock enable: cke high activa tes, and cke low deactivates internal clock signals, and device input buffers and output drivers. taking cke low provides precharge power down and self refresh operation (all ba nks idle), or active power down (row active in any bank). cke is synchronous for power down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit, and for output disable. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, /ck and cke are disabled during powe r down. input buffers, excluding cke are disabled during self refresh. cke is an sstl_2 input, but will detect an lvcmos low level after vdd is applied. /cs input chip select : enables or disables all inputs except ck, /ck, cke, dqs and dm. all com- mands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write or pre- charge command is being applied. a0 ~ a12 input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharg ed, the bank is selected by ba0, ba1. the address inputs also provide the op code during a mode register set command. ba0 and ba1 define which mode register is loaded during the mode register set command (mrs or emrs). /ras, /cas, /we input command inputs: /ras, /cas and /we (along with /cs) define the command being entered. ldm, udm input input data mask: dm(ldm,udm) is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. althou gh dm pins are input only, the dm loading matches the dq and dqs loading. ldm corresponds to the data on dq0-q7; udm corre- sponds to the data on dq8-q15. ldqs, udqs i/o data strobe: output with read data, input with write data. edge aligned with read data, centered in write data. used to capture wr ite data. ldqs corresponds to the data on dq0-q7; udqs corresponds to the data on dq8-q15. dq0 ~ dq15 i/o data input / output pin : data bus v dd /v ss supply power supply for internal circuits and input buffers. v ddq /v ssq supply power supply for output buffers for noise immunity. v ref supply reference voltage for inputs for sstl interface. nc nc no connection.
rev. 0.5 / feb. 2006 6 1 HY5DU561622CTP functional block diagram 4banks x 4mbit x 16 i/o double data rate synchronous dram command decoder clk /clk cke /cs /ras /cas ldm udm address buffer a0-12 bank control 4mx16/bank0 column decoder column address counter sense amp 2-bit prefetch unit 4mx16 /bank1 4mx16 /bank2 4mx16 /bank3 mode register row decoder input buffer output buffer data strobe transmitter data strobe receiver ldqs,udqs ds write data register 2-bit prefetch unit ds dq[0:15] 64 32 16 32 ba0,ba1 dll block clk_dll clk, /clk mode register
rev. 0.5 / feb. 2006 7 1 HY5DU561622CTP simplified command truth table command cken-1 cken cs ras cas we addr a10/ ap ba note extended mode register seth x llll op code 1,2 mode register set h x llll op code 1,2 device deselect hx hxxx x1 no operation lhhh bank active h x l l h h ra v 1 read h x lhlhca l v 1 read with autoprecharge h1,3 write hxlhllca l v 1 write with autoprecharge h1,4 precharge all banks hxllhlx hx1,5 precharge selected bank lv1 read burst stop h x l h h l x 1 auto refresh h h lllh x 1 self refresh entryh l lllh x 1 exit l h hxxx 1 lhhh precharge power down mode entry h l hxxx x 1 lhhh 1 exit l h hxxx 1 lhhh 1 active power down mode entry h l hxxx x 1 lvvv 1 exit l h x 1 note : 1. ldm/udm states are don?t care. refer to below write mask truth table. 2. op code(operand code) consists of a0~a12 and ba0~ba1 us ed for mode register setting during extended mrs or mrs. before entering mode register set mode, all banks must be in a precharge state and mrs command can be issued after trp period from prechagre command. 3. if a read with autoprecharge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+trp). 4. if a write with autoprecharge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+1+tdpl+trp). last data-in to prechage delay(tdpl) which is also called write recovery tim e (twr) is needed to guarantee that the last data has been completely written. 5. if a10/ap is high when precharge command being issued, ba0/ba1 are ignored and all banks are selected to be precharged. ( h=logic high level, l=logic low level, x=don?t care, v=va lid data input, op code=operand code, nop=no operation )
rev. 0.5 / feb. 2006 8 1 HY5DU561622CTP write mask truth table function cken-1 cken /cs, /ras, /cas, /we ldm udm addr a10/ ap ba note data write h x x l l x 1,2 data-in mask h x x h h x 1,2 lower byte write / upper byte-in mask hx x lh x 1,2 upper byte write / lower byte-in mask hx x hl x 1,2 note : 1. write mask command masks burst write data with reference to ldqs/udqs(data strobes) and it is not related with read data. 2. ldm and udm control lower byte(dq0~7) and upper byte(dq8~15) respectively.
rev. 0.5 / feb. 2006 9 1 HY5DU561622CTP operation command truth table - i current state /cs /ras /cas /we address command action idle hxxx x dsel nop or power down 3 lhhh x nop nop or power down 3 lhhl x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4 l h l l ba, ca, ap write/writeap illegal 4 l l h h ba, ra act row activation llhl ba, ap pre/pall nop lllh x aref/sref auto refresh or self refresh 5 l l l l opcode mrs mode register set row active hxxx x dsel nop lhhh x nop nop lhhl x bst illegal 4 l h l h ba, ca, ap read/readap begin read : optional ap 6 l h l l ba, ca, ap write/writeap begin write : optional ap 6 llhhba, ra act illegal 4 llhl ba, ap pre/pall precharge 7 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 read h x x x x dsel continue burst to end l h h h x nop continue burst to end l h h l x bst terminate burst l h l h ba, ca, ap read/readap term burst, new read:optional ap 8 l h l l ba, ca, ap write/writeap illegal llhhba, ra act illegal 4 l l h l ba, ap pre/pall term burst, precharge lllh x aref/sref illegal 11 llllopcode mrs illegal 11 write h x x x x dsel continue burst to end l h h h x nop continue burst to end lhhl x bst illegal 4 l h l h ba, ca, ap read/readap term burst, new read:optional ap 8 l h l l ba, ca, ap write/writeap term burst, new write:optional ap
rev. 0.5 / feb. 2006 10 1 HY5DU561622CTP operation command truth table - ii current state /cs /ras /cas /we address command action write llhhba, ra act illegal 4 l l h l ba, ap pre/pall term burst, precharge lllh x aref/sref illegal 11 llllopcode mrs illegal 11 read with autopre- charge h x x x x dsel continue burst to end l h h h x nop continue burst to end lhhl x bst illegal l h l h ba, ca, ap read/readap illegal 10 l h l l ba, ca, ap write/writeap illegal 10 llhhba, ra act illegal 4,10 llhl ba, ap pre/pall illegal 4,10 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 write autopre- charge h x x x x dsel continue burst to end l h h h x nop continue burst to end lhhl x bst illegal l h l h ba, ca, ap read/readap illegal 10 l h l l ba, ca, ap write/writeap illegal 10 llhhba, ra act illegal 4,10 llhl ba, ap pre/pall illegal 4,10 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 pre- charge h x x x x dsel nop-enter idle after trp l h h h x nop nop-enter idle after trp lhhl x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4,10 l h l l ba, ca, ap write/writeap illegal 4,10 llhhba, ra act illegal 4,10 l l h l ba, ap pre/pall nop-enter idle after trp lllh x aref/sref illegal 11 llllopcode mrs illegal 11
rev. 0.5 / feb. 2006 11 1 HY5DU561622CTP operation command truth table - iii current state /cs /ras /cas /we address command action row activating h x x x x dsel nop - enter row act after trcd l h h h x nop nop - enter row act after trcd lhhl x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4,10 l h l l ba, ca, ap write/writeap illegal 4,10 llhhba, ra act illegal 4,9,10 llhl ba, ap pre/pall illegal 4,10 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 write recovering h x x x x dsel nop - enter row act after twr l h h h x nop nop - enter row act after twr lhhl x bst illegal 4 l h l h ba, ca, ap read/readap illegal l h l l ba, ca, ap write/writeap illegal llhhba, ra act illegal 4,10 llhl ba, ap pre/pall illegal 4,11 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 write recovering with autopre- charge h x x x x dsel nop - enter precharge after tdpl l h h h x nop nop - enter precharge after tdpl lhhl x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4,8,10 l h l l ba, ca, ap write/writeap illegal 4,10 llhhba, ra act illegal 4,10 llhl ba, ap pre/pall illegal 4,11 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 refreshing h x x x x dsel nop - enter idle after trc l h h h x nop nop - enter idle after trc lhhl x bst illegal 11 l h l h ba, ca, ap read/readap illegal 11
rev. 0.5 / feb. 2006 12 1 HY5DU561622CTP operation command truth table - iv note : 1. h - logic high level, l - logic low level, x - don?t care, v - valid data input, ba - bank address, ap - autoprecharge address, ca - column address, ra - row address, nop - no operation. 2. all entries assume that cke was active(high level) during the preceding clock cycle. 3. if both banks are idle and cke is inactive(low level), then in power down mode. 4. illegal to bank in specified state. function may be legal in the bank indicated by bank address(ba) depending on the state of that bank. 5. if both banks are idle and cke is inactive(low level), then self refresh mode. 6. illegal if trcd is not met. 7. illegal if tras is not met. 8. must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. illegal if trrd is not met. 10. illegal for single bank, but legal for other banks in multi-bank devices. 11. illegal for all banks. current state /cs /ras /cas /we address command action write l h l l ba, ca, ap write/writeap illegal 11 llhhba, ra act illegal 11 llhl ba, ap pre/pall illegal 11 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 mode register accessing h x x x x dsel nop - enter idle after tmrd l h h h x nop nop - enter idle after tmrd lhhl x bst illegal 11 l h l h ba, ca, ap read/readap illegal 11 l h l l ba, ca, ap write/writeap illegal 11 llhhba, ra act illegal 11 llhl ba, ap pre/pall illegal 11 lllh x aref/sref illegal 11 llllopcode mrs illegal 11
rev. 0.5 / feb. 2006 13 1 HY5DU561622CTP cke function truth table note : when cke=l, all dq and dqs must be in hi-z state. 1. cke and /cs must be kept high for a minimum of 200 stable input clocks before issuing any command. 2. all command can be stored after 2 clocks from low to high transition of cke. 3. illegal if ck is suspended or stopped during the power down mode. 4. self refresh can be entered only from the all banks idle state. 5. disabling ck may cause malfunction of any bank which is in active state. current state cken-1 cken /cs /ras /cas /we /add action self refresh 1 h xxxxxx invalid l h h x x x x exit self refresh, enter idle after tsrex l h l h h h x exit self refresh, enter idle after tsrex lhlhhlx illegal lhlhlxx illegal l hllxxx illegal l lxxxxx nop, continue self refresh power down 2 h xxxxxx invalid l h h x x x x exit power down, enter idle l h l h h h x exit power down, enter idle lhlhhlx illegal lhlhlxx illegal l hllxxx illegal l lxxxxxnop, continue power down mode all banks idle 4 h h x x x x x see operation command truth table h llllhx enter self refresh h l h x x x x exit power down h l l h h h x exit power down hllhhlx illegal hllhlxx illegal hlllhxx illegal h lllllx illegal l lxxxxx nop any state other than above h h x x x x x see operation command truth table h lxxxxx illegal 5 l hxxxxx invalid l lxxxxx invalid
rev. 0.5 / feb. 2006 14 1 HY5DU561622CTP simplified state diagram mrs sref srex pden pdex act aref pdex pden bst read write write writeap writeap read readap readap pre(pall) pre(pall) pre(pall) command input automatic sequence idle auto refresh pre- charge power-up power applied mode register set power down write with autopre- charge power down write read with autopre- charge bank active read self refresh
rev. 0.5 / feb. 2006 15 1 HY5DU561622CTP power-up sequence and device initialization ddr sdrams must be powered up and initialized in a pred efined manner. operational pr ocedures other than those specified may result in undefined operation. except for ck e, inputs are not recognized as valid until after vref is applied. cke is an sstl_2 input, but will detect an lv cmos low level after vdd is ap plied. maintaining an lvcmos low level on cke during power-up is required to guarant ee that the dq and dqs outputs will be in the high-z state, where they will remain until driven in normal operation (by a read access). after all power supply and reference volt- ages are stable, and the clock is stable, the ddr sdram requ ires a 200us delay prior to applying an executable com- mand. once the 200us delay has been satisfied, a deselect or nop command should be applied, and cke should be brought high. following the nop command, a precharg e all command should be applied. next a extended mode register set command should be issued for the ex tended mode register, to enable the dll, then a mode register set command should be issued for the mode re gister, to reset the dll, and to program the operating parameters. after the dll reset, txsrd(dll locking time) sh ould be satisfied for read command. after the mode reg- ister set command, a precharge all command should be a pplied, placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. additionally, a mode register set command for the mode register, with the reset dll bit deactivated lo w (i.e. to program operating parameters without resetting the dll) must be performed. following these cycl es, the ddr sdram is ready for normal operation. 1. apply power - vdd, vddq, vtt, vref in the following po wer up sequencing and attemp t to maintain cke at lvc- mos low state. (all the other input pins may be undefined. no power sequencing is specified during power up or power down given the following cirteria : ? vdd and vddq are driven from a single power converter output. ? vtt is limited to 1.44v (reflecting vddq(max )/2 + 50mv vref variation + 40mv vtt variation). ?vref tracks vddq/2. ? a minimum resistance of 42 ohms (22 ohm series resist or + 22 ohm parallel resistor - 5% tolerance) limits the input current from the vtt supply into any pin. if the above criteria cannot be met by the system design, then the following sequencing and voltage relationship must be adhered to during power up : 2. start clock and maintain stable clock for a minimum of 200usec. 3. after stable power and clock, apply nop condition and take cke high. 4. issue extended mode register set (emrs) to enable dll. 5. issue mode register set (mrs) to reset dll and set devi ce to idle state with bit a8=high. (an additional 200 cycles(txsrd) of clock are required for locking dll) 6. issue precharge commands for all banks of the device. voltage description sequencing voltage relationship to avoid latch-up vddq after or with vdd < vdd + 0.3v vtt after or with vddq < vddq + 0.3v vref after or with vddq < vddq + 0.3v
rev. 0.5 / feb. 2006 16 1 HY5DU561622CTP 7. issue 2 or more auto refresh commands. 8. issue a mode register set command to initialize the mode register with bit a8 = low. power-up sequence code code code code code code code code code code code code code code code nop pre mrs emrs pre nop mrs aref act rd vdd vddq vtt vref /clk clk cke cmd dm addr a10 ba0, ba1 dqs dq's lvcmos low level tis tih tvtd t=200usec trp tmrd trp trfc tmrd txsrd* read non-read command power up vdd and ck stable precharge all emrs set mrs set reset dll (with a8=h) precharge all 2 or more auto refresh mrs set (with a8=l) * 200 cycle(txsrd) of ck are required (for dll locking) before read command tmrd
rev. 0.5 / feb. 2006 17 1 HY5DU561622CTP mode register set (mrs) the mode register is used to store the various operating mo des such as /cas latency, addressing mode, burst length, burst type, test mode, dll reset. the mode register is pr ogram via mrs command. this command is issued by the low signals of /ras, /cas, /cs, /we and ba0. this command can be issued only when all bank s are in idle state and cke must be high at least one cycle before the mode register set command can be issued. two cycles are required to write the data in mode register. during the the mrs cycle, an y command cannot be issued. once mode register field is determined, the information will be held until resetted by another mrs command. ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 rfu dr tm cas latency bt burst length a2 a1 a0 burst length sequential interleave 000reservedreserved 001 2 2 010 4 4 011 8 8 100reservedreserved 101reservedreserved 110reservedreserved 111reservedreserved a3 burst type 0 sequential 1 interleave a6 a5 a4 cas latency 000 reserved 001 reserved 010 reserved 011 3 100 4 101 5 110 reserved 111 reserved a7 test mode 0normal 1test a8 dll reset 0no 1yes ba0 mrs type 0mrs 1emrs
rev. 0.5 / feb. 2006 18 1 HY5DU561622CTP burst definition burst length & type read and write accesses to the ddr sdra m are burst oriented, with the burst length being programmable. the burst length determines the maximum number of column locations that can be accessed for a given read or write com- mand. burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operatio n or incompatibility with future versions may result. when a read or write command is issued, a block of column s equal to the burst length is effectively selected. all accesses for that burst take place within this block, mean ing that the burst wraps within the block if a boundary is reached. the block is uniquely selected by a1-ai when the burs t length is set to two, by a2-ai when the burst length is set to four and by a3-ai when the burst length is set to eigh t (where ai is the most significant column address bit for a given configuration). the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. accesses within a given burst may be programmed to be either sequential or interleaved; th is is referred to as the burst type and is selected via bit a3. the ordering of acce sses within a burst is determined by the burst length, the burst type and the starting column addres s, as shown in burst definitionon table cas latency the read latency or cas latency is the delay in clock cy cles between the registration of a read command and the burst length starting address (a2,a1,a0) sequential interleave 2 xx0 0, 1 0, 1 xx1 1, 0 1, 0 4 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 8 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 0, 1, 2, 3, 4, 5, 6, 7 7, 6, 5, 4, 3, 2, 1, 0
rev. 0.5 / feb. 2006 19 1 HY5DU561622CTP availability of the first burst of output data . the latency can be programmed 3 or 4 clocks. if a read command is registered at clock edge n, and the la tency is m clocks, the data is available nominally coincident with clock edge n + m. reserved states should not be used as unknown operatio n or incompatibility with future versions may result. dll reset the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon return- ing to normal operation after having disabled the dll for th e purpose of debug or evaluation. the dll is automatically disabled when entering self refresh oper ation and is automatically re-enabled upon exit of self refresh operation. any time the dll is enabled, 200 clock cycles must occur to al low time for the internal cloc k to lock to the externally applied clock before an any command can be issued. output driver impedance control the hy5du561622ct supports full, half strength driver and matched impedance driver, intended for lighter load and/ or point-to-point environments. the full drive strength for al l output is specified to be sstl_2, class ii. half strength driver is to define about 50% of full drive strength and matched impedance driver, about 30% of full drive strength.
rev. 0.5 / feb. 2006 20 1 HY5DU561622CTP extended mode register set (emrs) the extended mode register controls fu nctions beyond those controlled by the mode register; these additional func- tions include dll enable/disable, output dr iver strength selection(optional). thes e functions are contro lled via the bits shown below. the extended mode register is programmed via the mode register set command ( ba0=1 and ba1=0) and will retain the stored information until it is programmed again or the device loses power. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subseque nt operation. violating either of these requirements will result in unspecified operation. ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 rfu* ds rfu* ds dll a0 dll enable 0enable 1diable ba0 mrs type 0mrs 1emrs * all bits in rfu address fields must be programmed to zero, all other states are reserved for future usage. a6 a1 output driver impedance control 00 full 0 1 half 10 rfu* 1 1 matched impedance (weak)
rev. 0.5 / feb. 2006 21 1 HY5DU561622CTP absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability dc operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. v ddq must not exceed the level of v dd . 2. v il (min) is acceptable -1.5v ac pulse width with 5ns of duration. 3. vih (max) is acceptable vddq + 1.5v ac pulse width with < 5ns of duration 4. v ref is expected to be equal to 0.5*v ddq of the transmitting device, and to track variations in the dc level of the same. peak to peak noise on v ref may not exceed 2% of the dc value. 5. supports 250/200/166 mhz. 6. supports 300/275 mhz. 7. supports 350mhz. dc characteristics i (ta=0 to 70oc, voltage referenced to v ss = 0v) parameter symbol rating unit ambient temperature t a 0 ~ 70 o c storage temperature t stg -55 ~ 125 o c voltage on any pin relative to v ss v in , v out -0.5 ~ 3.6 v voltage on v dd relative to v ss v dd -0.5 ~ 3.6 v voltage on v ddq relative to v ss v ddq -0.5 ~ 3.6 v output short circuit current i os 50 ma power dissipation p d 1w soldering temperature ? time t solder 260 ? 10 o c ? sec parameter symbol min typ. max unit note power supply voltage v dd 2.375 2.5 2.625 v 5 power supply voltage v dd 2.5 2.6 2.9 v 6 power supply voltage v dd 2.7 2.8 2.9 v 7 power supply voltage v ddq 2.375 2.5 2.625 v 5, 1 power supply voltage v ddq 2.5 2.6 2.9 v 6, 1 power supply voltage v ddq 2.7 2.8 2.9 v 7, 1 input high voltage v ih v ref + 0.15 - v ddq + 0.3 v input low voltage v il -0.3 - v ref - 0.15 v 2 termination voltage v tt v ref - 0.04 v ref v ref + 0.04 v reference voltage v ref 0.49*v ddq 0.5*v ddq 0.51*v ddq v3 parameter symbol min. max unit note input leakage current i li -5 5 ua 1 output leakage current i lo -5 5 ua 2 output high voltage v oh v tt + 0.76 - v i oh = -15.2ma output low voltage v ol -v tt - 0.76 v i ol = +15.2ma note : 1. v in = 0 to 3.6v, all other pins are not tested under v in = 0v. 2. d out is disabled, v out = 0 to 2.7v
rev. 0.5 / feb. 2006 22 1 HY5DU561622CTP dc characteristics ii (ta=0 to 70 o c, voltage referenced to v ss = 0v) parameter symbol test condition speed unit note 28 33 36 4 5 6 operating current i dd1 one bank; active - read - precharge; burst length=4; trc=trc(min); tck=tck(min); address and control inputs changing once per clock cycle; iout=0ma 180 180 170 160 150 150 ma precharge power down standby current i dd2p all banks idle; power down mode; cke=low, tck=tck(min) 20 ma idle standby current i dd2f /cs=high, all banks idle; tck=tck(min); cke=high; address and control inputs changing once per clock cycle. vin=vref for dq, dqs and dm 100 100 90 80 70 70 ma active power down standby current i dd3p one bank active; power down mode ; cke=low, tck=tck(min) 45 45 40 35 30 30 ma active standby current i dd3n /cs=high; cke=high; one bank; active-precharge; trc=tras(max); tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 110 110 100 90 80 80 ma operating current i dd4r burst=2;reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); iout=0ma 260 260 240 220 200 200 ma idd4w burst=2; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle ma auto refresh current i dd5 trc=trfc(min); all banks active 240 240 220 200 180 180 ma self refresh current i dd6 cke=<0.2v; external clock on; tck=tck(min) 4ma
rev. 0.5 / feb. 2006 23 1 HY5DU561622CTP ac operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. vid is the magnitude of the difference betw een the input level on ck and the input on ck. 2. the value of vix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. ac operating test conditions (ta=0 to 70 o c, voltage referenced to vss = 0v) parameter symbol min max unit note input high (logic 1) voltag e, dq, dqs and dm signals v ih(ac) v ref + 0.35 v input low (logic 0) voltage, dq, dqs and dm signals v il(ac) v ref - 0.35 v input differential voltage, ck and /ck inputs v id(ac) 0.7 v ddq + 0.6 v 1 input crossing point voltage, ck and /ck inputs v ix(ac) 0.5*v ddq -0.2 0.5*v ddq +0.2 v 2 parameter value unit reference voltage v ddq x 0.5 v termination voltage v ddq x 0.5 v ac input high level voltage (v ih , min) v ref + 0.35 v ac input low level voltage (v il , max) v ref - 0.35 v input timing measurement reference level voltage v ref v output timing measurement reference level voltage v tt v input signal maximum peak swing 1.5 v input minimum signal slew rate 1 v/ns termination resistor (r t )50 ? series resistor (r s )25 ? output load capacitance for access time measurement (c l )30 pf
rev. 0.5 / feb. 2006 24 1 HY5DU561622CTP ac characteristics - i (ac operating conditions unless otherwise noted) parameter symbol 28 33 36 unit note min max min max min max row cycle time (manual precharge) t rc 20 - 18 - 16 - ck row cycle time (auto precharge) trc_apcg 21 - 19 - 18 - ck auto refresh row cycle time t rfc 24 - 22 - 20 - ck row active time t ras 40 70k 40 70k 40 70k ns row address to column address delay t rcdrd 6-6-5-ck t rcdwt 2-2-2-ck row active to row active delay t rrd 2-2-2-ck column address to column address delay t ccd 1-1-1-ck row precharge time t rp 6-6-5-ck last data-in to precharge delay (write recovery time : twr) t dpl 4-3-3-ck last data-in to read command t drl 2-2-2-ck auto precharge write recovery + precharge time t dal 10-9-8-ck system clock cycle time cl = 4.0 t ck 2.8 7.0 3.3 7.0 3.6 7.0 ns cl = 3.0 ------ns clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 ck clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 ck data-out edge to clock edge skew t ac -0.7 0.7 -0.7 0.7 -0.7 0.7 ns dqs-out edge to clock edge skew t dqsck -0.7 0.7 -0.7 0.7 -0.7 0.7 ns dqs-out edge to data-out edge skew t dqsq -0.4-0.4-0.4ns data-out hold time from dqs t qh t hpmin -t qhs - t hpmin -t qhs - t hpmin -t qhs -ns1, 6 clock half period t hp t ch/l min - t ch/l min - t ch/l min -ns1, 5 data hold skew factor t qhs -0.4-0.4-0.4ns6 input setup time t is 0.75 - 0.75 - 0.75 - ns 2 input hold time t ih 0.75 - 0.75 - 0.75 - ns 2 write dqs high level width t dqsh 0.4 0.6 0.4 0.6 0.4 0.6 ck write dqs low level width t dqsl 0.4 0.6 0.4 0.6 0.4 0.6 ck clock to first rising edge of dqs-in t dqss 0.85 1.15 0.85 1.15 0.85 1.15 ck data-in setup time to dqs-in (dq & dm) t ds 0.4-0.4-0.4-ns3
rev. 0.5 / feb. 2006 25 1 HY5DU561622CTP data-in hold time to dqs-in (dq & dm) t dh 0.4-0.4-0.4-ns3 read dqs preamble time t rpre 0.9 1.1 0.9 1.1 0.9 1.1 ck read dqs postamble time t rpst 0.4 0.6 0.4 0.6 0.4 0.6 ck write dqs preamble setup time t wpres 0-0-0-ns write dqs preamble hold time t wpreh 1.5-1.5-1.5-ns write dqs postamble time t wpst 0.4 0.6 0.4 0.6 0.4 0.6 ck mode register set delay t mrd 2-2-2-ck exit self refresh to any execute command t xsc 200 - 200 - 200 - ck 4 power down exit time except read command t pdex 1tck + tis - 1tck + tis - 1tck + tis -ck read command tpdex_rd 2tck + tis - 2tck + tis - 2tck + tis -ck average periodic refresh interval t refi -7.8-7.8-7.8us parameter symbol 28 33 36 unit note min max min max min max
rev. 0.5 / feb. 2006 26 1 HY5DU561622CTP ac characteristics - i (ac operating conditions unless otherwise noted) parameter symbol 4 5 6 unit note min max min max min max row cycle time (manual precharge) t rc 15 - 12 - 11 - ck row cycle time (auto precharge) trc_apcg 17 - 14 - 11 - ck auto refresh row cycle time t rfc 18 - 14 - 12 - ck row active time t ras 40 70k 40 70k 40 70k ns row address to column address delay t rcdrd 5-4-4-ck t rcdwt 2-2-2-ck row active to row active delay t rrd 2-2-2-ck column address to column address delay t ccd 1-1-1-ck row precharge time t rp 5-4-4-ck last data-in to precharge delay (write recovery time : twr) t dpl 3-3-3-ck last data-in to read command t drl 2-2-2-ck auto precharge write recovery + precharge time t dal 8-7-6-ck system clock cycle time cl = 4.0 t ck 4.07.0----ns cl = 3.0 - - 5.0 7.0 6.0 7.0 ns clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 ck clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 ck data-out edge to clock edge skew t ac -0.7 0.7 -0.7 0.7 -0.7 0.7 ns dqs-out edge to clock edge skew t dqsck -0.7 0.7 -0.7 0.7 -0.7 0.7 ns dqs-out edge to data-out edge skew t dqsq - 0.4 - 0.45 - 0.45 ns data-out hold time from dqs t qh t hpmin -t qhs - t hpmin -t qhs - t hpmin -t qhs -ns1, 6 clock half period t hp t ch/l min - t ch/l min - t ch/l min -ns1, 5 data hold skew factor t qhs -0.4-0.5-0.5ns6 input setup time t is 0.75 - 0.75 - 0.75 - ns 2 input hold time t ih 0.75 - 0.75 - 0.75 - ns 2 write dqs high level width t dqsh 0.4 0.6 0.4 0.6 0.4 0.6 ck write dqs low level width t dqsl 0.4 0.6 0.4 0.6 0.4 0.6 ck clock to first rising edge of dqs-in t dqss 0.85 1.15 0.75 1.25 0.75 1.25 ck data-in setup time to dqs-in (dq & dm) t ds 0.4 - 0.4 - 0.4 - ns 3
rev. 0.5 / feb. 2006 27 1 HY5DU561622CTP n ote : 1. this calculation accounts for tdqsq(max), the pulse width distortion of on-chip circuit and jitter. 2. data sampled at the rising edges of the cloc k : a0~a12, ba0~ba1, cke, /cs, /ras, /cas, /we. 3. data latched at both rising and falling edges of data strobes(ldqs/udqs) : dq, ldm/udm. 4. minimum of 200 cycles of stable input clocks after self refresh exit command, where cke is held high, is required to complet e self refresh exit and lock the internal dll circuit of ddr sdram. 5. min (tcl, tch) refers to the smaller of the actual clock low ti me and the actual cloc k high time as provided to the device ( i.e. this value can be greater than the mini mum specification limits for tcl and tch). 6. thp = minimum half clock period for any given cycle and is de fined by clock high or clock low (tch, tcl). tqhs consists of tdqsqmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects, and p-chan nel to n-channel variation of the output drivers. 7. dqs, dm and dq input slew rate is specified to prevent double clocking of data and preserve setup and hold times. signal transitions through the dc region must be monotonic. data-in hold time to dqs-in (dq & dm) t dh 0.4 - 0.4 - 0.4 - ns 3 read dqs preamble time t rpre 0.9 1.1 0.9 1.1 0.9 1.1 ck read dqs postamble time t rpst 0.4 0.6 0.4 0.6 0.4 0.6 ck write dqs preamble setup time t wpres 0-0-0-ns write dqs preamble hold time t wpreh 1.5 - 1.5 - 1.5 - ns write dqs postamble time t wpst 0.4 0.6 0.4 0.6 0.4 0.6 ck mode register set delay t mrd 2-2-2-ck exit self refresh to any execute command t xsc 200 - 200 - 200 - ck 4 power down exit time except read command t pdex 1tck + tis - 1tck + tis - 1tck + tis -ck read command tpdex_rd 2tck + tis - 2tck + tis - 2tck + tis -ck average periodic refresh interval t refi -7.8-7.8-7.8us parameter symbol 4 5 6 unit note min max min max min max
rev. 0.5 / feb. 2006 28 1 HY5DU561622CTP ac characteristics - ii frequency cl trc (manual precharge) trc_apcg (auto precharge) trfc tras trcdrd trcdwr trp tdal unit 350mhz (2.8ns) 4 20 21 24 40ns 6 2 6 10 tck 300mhz (3.3ns) 4 18 16 22 40ns 6 2 6 9 tck 275mhz (3.6ns) 4 16 18 20 40ns 5 2 5 8 tck 250mhz (4.0ns) 4 15 17 18 40ns 5 2 5 8 tck 200mhz (5.0ns) 3 12 14 14 40ns 4 2 4 7 tck 166mhz (6.0ns) 3 11 11 12 40ns 4 2 4 6 tck
rev. 0.5 / feb. 2006 29 1 HY5DU561622CTP capacitance (t a =25 o c, f=1mhz ) note : 1. v dd = min. to max., v ddq = 2.3v to 2.7v, v o dc = v ddq /2, v o peak-to-peak = 0.2v 2. pins not under test are tied to gnd. 3. these values are guaranteed by desi gn and are tested on a sample basis only. output load circuit parameter pin symbol min max unit input clock capacitance ck, ck c ck 2.0 3.0 pf input capacitance all other input-only pins c in 2.0 3.0 pf input / output capacitanc dq, dqs, dm c io 4.0 5.0 pf v ref v tt r t =50 ? zo=50 ? c l =30pf output
rev. 0.5 / feb. 2006 30 1 HY5DU561622CTP 10.26 (0.404) 10.05 (0.396) 11.94 (0.470) 11.79 (0.462) 22.33 (0.879) 22.12 (0.871) 1.194 (0.0470) 0.991 (0.0390) 0.65 (0.0256) bsc 0.35 (0.0138) 0.25 (0.0098) 0.15 (0.0059) 0.05 (0.0020) base plane seating plane 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047) 0 ~ 5 deg. unit : mm(inch) package information 400mil 66pin thin small outline package note : package do not mold protrusion. allowable protrusion of both sides is 0.4mm.

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